This invention relates to a new semiconductor memory device, and more specifically, to a new circuit element arrangement of a semiconductor memory device.
FIGS. 4 and 5 show examples of the layout of circuit elements in conventional semiconductor memory devices. In FIG. 4, single memory cell array 2 is disposed in the center portion of the semiconductor substrate 1, and two shift registers 4,4, used as serial memories, are contiguously arranged on both sides of said memory cell array 2. A control signal from a control signal generator 62 is transmitted to said shift registers 4,4 through control signal lines 52,52. Input or output data is transmitted between said shift registers 4,4 and an input/output (I/O) circuit 64. In FIG. 5, a memory cell array is separated into two blocks 2,2 on the substrate 1. A single shift register 4 is disposed on one side of said memory cell arrays 2,2 and a plurality of data lines 65 connect said memory cell arrays 2,2 and to said shift register 4. A control signal from the control signal generator 62 is transmitted to said shift register 4 through the control signal line 52. Input or output data is transmitted between said shift register 4 and the I/O circuit 64.
The basic operation of the semiconductor memory devices of FIGS. 4 and 5 is as follows.
In a read-out mode, multi-bit data read out from the memory cell array(s) 2 is temporarily stored in the shift register(s) 4, and then the data is transmitted to the I/O terminals (not shown) of the device through the I/O circuit 64. Such an operation is controlled by the control signal from the control signal generator 62. In a write mode, the data from the I/O circuit 64 is temporarily stored in the shift register(s) 4, and then the data is written in the memory cell array(s) 2. Such an operation is also controlled by the control signal from the control signal generator 62.
However, in the layout of the circuit elements shown in FIG. 4, since the length of the control signal lines 52,52 is quite long, the stray capacitance of said lines tends to increase, and therefore, the delay of a signal transmitted along said lines 52,52 tends to become long. As a result, the input/output operations and the data transfer operations of the shift registers 4,4 become slower, the high speed operation of the memory device is sacrificed. In view of the recent tendency for the memory capacity to become large, the size of the substrate of semiconductor memory device has tended to become larger. In such a case, the above-mentioned problem becomes quite serious. On the other hand, in case of the layout shown in FIG. 5, the length of the control signal line 52 is shorter, and therefore, so far as the shift register operation is concerned, there are few factors which make its operation speed slow. However, the length of the data lines 65 which connect the memory cell arrays 2,2 and the shift register 4 have to become longer. Therefore, the stray capacitance of the data lines 65 tends to increase, and this obstructs the high speed operation of the memory device. Furthermore, in FIG. 5, since a plurality of data lines have to be laid with close mutual distances in a long area, the noise on the data lines 65 due to the parasitic capacitance effect between the data lines can ot be neglected for the stable operations of the device.